1. Field of the Invention
The present invention relates to a multi port SRAM (Static Random Access Memory) including MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and, more particularly, to a technique for reading and writing data from and into memory cells of the SRAM.
2. Description of the Background Art
In an integrated circuit, an SRAM is used to cache data or instructions, i.e., to function to temporarily hold data therein for transmission of data to a CPU (Central Processing Unit) in timed relation to the CPU and to store the state of a sequential circuit therein. In recent years, emphasis has been placed on the rate at which data is written into and read from the memory. To increase a memory bandwidth, there has been proposed a technique in which a plurality of I/O ports are provided to the memory cells of the SRAM. Examples of this technique include a dual port static memory cell having one read port and one write port, and a multi port static memory cell having a multiplicity of read ports and a multiplicity of write ports.
FIG. 51 conceptually illustrates a configuration of a background art SRAM including a memory cell array and its peripheral components. Memory cells in the array are disposed in a matrix having m rows and n columns, and a memory cell in the i-th row, j-th column is designated by MCij. In FIG. 51 is shown the reference character MC13 designating a memory cell disposed in the first row, the third column.
The SRAM shown in FIG. 51 is configured to have word lines extending along the rows and bit lines extending along the columns. A word line decoder 3 is connected to word line groups 30i (i=1, 2, 3, . . . , mxe2x88x921, m), and selectively activates a word line group 30i corresponding to a row address RA inputted thereto. A bit line decoder 4 is connected to bit line groups 40j (j=1, 2, 3, . . . , nxe2x88x921, n), and selectively activates a bit line group 40j corresponding to a column address CA inputted thereto.
The word line groups 30i and the bit line groups 40j intersect each other at the memory cells MCij. In other words, a common word line group is provided in corresponding relation to a plurality of memory cells arranged along each row, and a common bit line group is provided in corresponding relation to a plurality of memory cells arranged along each column.
Each of the word line groups 30i includes a write word line 31i, a read word line 33i, and a read complement word line 32i. The read word line 33i and the read complement word line 32i constitute a read word line pair. Each of the bit line groups 40j includes a write data bit line 41j, a write data complement bit line 42j, and a read data bit line 43j. The write data bit line 41j and the write data complement bit line 42j constitute a write data bit line pair.
FIG. 52 is a circuit diagram illustrating a common structure of every memory cell MC. Since the structure of the memory cells MC is not dependent basically upon the row and column locations (i, j), the subscripts denoting the row and column locations are omitted in FIG. 52.
The memory cell MC shown in FIG. 52 comprises a storage part (referred to hereinafter as a xe2x80x9cstorage cellxe2x80x9d) SC having a pair of inverters L1 and L2 comprising a cross-coupled latch circuit, a read circuit RK, and access transistors QN3 and QN4.
In the storage cell SC, the inverter L1 has transistors QP1 and QN1 connected in series, and the inverter L2 has transistors QP2 and QN2 connected in series. The read circuit RK comprises a tristate inverter having transistors QP3, QP4, QN5, QN6 connected in series.
N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the transistors QN1 to QN6, and P-type MOSFETs are used as the transistors QP1 to QP4. For example, the N-type MOSFETs are of a surface-channel type, and the P-type MOSFETs are of a surface-channel or buried-channel type.
The storage cell SC further comprises a pair of nodes N1 and N2 which have a pair of storage states: the nodes N1 and N2 are xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d respectively, and vice versa. A xe2x80x9chighxe2x80x9d means a logic corresponding to a potential higher than (VDD+VSS)/2, and a xe2x80x9clowxe2x80x9d means a logic corresponding to a potential lower than (VDD+VSS)/2 where a ground is often selected as the potential VSS. A xe2x80x9chighxe2x80x9d and a xe2x80x9clowxe2x80x9d mean not only the logics but also potentials corresponding to the respective logics. Which of the xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d states represents a xe2x80x9c1xe2x80x9d as a bit of the SRAM and which represents a xe2x80x9c0xe2x80x9d is a matter of design choice.
The N-type MOSFET turns on when a xe2x80x9chighxe2x80x9d is applied to the gate thereof, and turns off when a xe2x80x9clowxe2x80x9d is applied thereto. The P-type MOSFET turns on when a xe2x80x9clowxe2x80x9d is applied to the gate thereof, and turns off when a xe2x80x9chighxe2x80x9d is applied thereto. In an xe2x80x9conxe2x80x9d state, current flows between the source and the drain of the MOSFET to provide electrical conduction therebetween. In an xe2x80x9coffxe2x80x9d state, there is electrical disconnection between the source and the drain of the MOSFET and almost no current flows therebetween.
The node N1 is the input of the inverter L2, and a potential corresponding to a logic complementary to the logic corresponding to the potential at the node N1 is outputted to the node N2. The node N2 is the input of the inverter L1, and the inverted bit of a logic complementary to the logic corresponding to the potential at the node N2 is outputted to the node N1. Thus, there are a pair of storage states corresponding to complementary logics.
The access transistor QN3 is connected at nodes N1 and N4 to the storage cell SC and the write data bit line 41, respectively. The access transistor QN4 is connected at nodes N2 and N5 to the storage cell SC and the write data complement bit line 42, respectively. The gates of the respective access transistors QN3 and QN4 are connected commonly to the write word line 31.
In the read circuit RK, the drains of the respective transistors QP4 and QN5 are connected commonly to a node N3. The gates of the respective transistors QP3 and QN6 are connected commonly to the node N1. The gates of the transistors QP4 and QN5 are connected to the read complement word line 32 and the read word line 33, respectively. As described above, a dual port static memory cell is used as the memory cell MC.
For reading data from the memory cell MC, complementary logics are placed on the read word line 33 and the read complement word line 32. The read word line 33 and the read complement word line 32 corresponding to a row including the memory cell MC to be read are driven high and low, respectively, whereas the read word lines 33 and the read complement word lines 32 corresponding to the other rows are driven low and high, respectively.
Thus, both of the transistors QP4 and QN5 of the read circuit RK in the memory cell MC to be read turn on. This causes an inverter comprised of the transistors QP3 and QN6 to apply a value complementary to the value at the node N1 through the node N3 to the read data bit line 43. On the other hand, the transistors QP4 and QN5 of the read circuit RK in each of the memory cells MC which are not to be read turn off. This disconnects the read data bit line 43 from the storage cell SC in each of the memory cells MC which are not to be read.
For writing data into the memory cell MC, the write word line 31 corresponding to a row including the memory cell MC to be written is driven high, whereas the write word lines 31 corresponding to the other rows are driven low.
Thus, both of the access transistors QN3 and QN4 in the memory cell MC to be written turn on. This connects the nodes N1 and N2 of the storage cell SC through the nodes N4 and N5 to the write data bit line 41 and the write data complement bit line 42, respectively. On the other hand, the access transistors QN3 and QN4 in each of the memory cells MC which are not to be written turn off. This disconnects the nodes N1 and N2 of the storage cell SC from the write data bit line 41 and the write data complement bit line 42 in each of the memory cells MC which are not to be written.
As described above, since the logics on the nodes N1 and N2 of the storage cell SC are in complementary relation, complementary logics are placed on the write data bit line 41 and the write data complement bit line 42 corresponding to a column including the memory cell MC to be written. Then, the logics placed on the write data bit line 41 and the write data complement bit line 42 are written into the nodes N1 and N2, respectively.
After the write operation, the write word line 31 is driven low to turn off the access transistors QN3 and QN4. This disconnects the storage cell SC from the write data bit line pair. Thus, the data held in the storage cell SC is not rewritten, and the storage cell SC is placed into a stand-by state.
In the above construction, when the write word line 31 is driven high during a write operation, the access transistors QN3 and QN4 in all of the memory cells MC disposed in the same row as the memory cell MC to be written turn on. Thus, in the memory cells MC which are disposed in the same row as the memory cell MC to be written but are not to be written, the nodes N1 and N2 are connected through the access transistors QN3 and QN4 to the write data bit line 41 and the write data complement bit line 42, respectively, during the write operation.
On the other hand, the write data bit lines 41 and the write data complement bit lines 42 corresponding to the columns including the memory cells MC which are not to be written are normally precharged to an equal potential. This precharge potential is, for example, VDD, (VDD+VSS)/2, or VSS. Therefore, depending on the potentials at the nodes N1 and N2 in each of these memory cells MC, one of the write data bit line 41 and the write data complement bit line 42 is pulled to VSS and the other is pulled to (VDDxe2x88x92Vthn) (assuming that the potential VDD is applied to the write word line 31 and the threshold voltage Vthn of the transistors QN3 and QN4 is greater than zero). The potential application through the nodes N1 and N2 to such precharged write data bit line pair gives rise to unwanted electric power consumption.
Additionally, the bit line pair to which the potential is applied by the storage cell SC in the above-mentioned manner is subjected to another precharge operation to prepare for the next write operation. This precharge operation also consumes unwanted electric power.
FIG. 53 is a circuit diagram showing a configuration of a memory cell MC proposed for preventing the above-mentioned power consumption and disclosed, for example, in U.S. Pat. No. 6,005,794.
NMOS transistors QN9 and QN10 are connected in series between the node N1 and a potential point providing the potential VSS (also referred to hereinafter as a xe2x80x9cpotential point VSSxe2x80x9d), e.g., a ground. The gate of the NMOS transistor QN9 is connected at the node N4 to the write data bit line 41, and the gate of the NMOS transistor QN10 is connected to the write word line 31. Similarly, NMOS transistors QN11 and QN12 are connected in series between the node N2 and the potential point VSS. The gate of the NMOS transistor QN11 is connected at the node N5 to the write data complement bit line 42, and the gate of the NMOS transistor QN12 is connected to the write word line 31.
The write word line 31 corresponding to the memory cell MC to be written (i.e., in a selected row) is driven high to turn on the transistors QN10 and QN12 during a write operation. Complementary logics are applied to the write data bit line 41 and the read data bit line 43 corresponding to the memory cell MC (i.e., in a selected column) to turn on one of the transistors QN9 and QN11. When the write data bit line 41 and the write data complement bit line 42 are high and low respectively, a logic xe2x80x9clowxe2x80x9d is placed on the node N1. This forces the node N2 high. Conversely, when the write data bit line 41 and the write data complement bit line 42 are low and high respectively, a logic xe2x80x9clowxe2x80x9d is placed on the node N2. This forces the node N1 high.
In such a write operation, all of the unselected write data bit line pairs are driven to the potential VSS. The transistors QN9 and QN11 are off in the memory cells MC which are not to be written. Therefore, in the memory cells MC disposed in the row corresponding to the selected write word line 31 which is high, the nodes N1 and N2 are not forced to any potential from externally of the storage cell SC. In other words, this is advantageous in preventing the above-mentioned unwanted power consumption.
However, this circuit presents a problem in that a write operation which changes the stored content of the storage cell SC requires much time. Specifically, this circuit forces one of the nodes N1 and N2 low from externally of the storage cell SC, but does not have the function of forcing the other node high from externally of the storage cell SC. For example, when inverting the nodes N1 and N2 which are high and low respectively into their complementary states, the transistors QN9 and QN10 turn on to attempt to discharge the node N1. However, since the node N2 is originally low and is not forced high from externally of the storage cell SC, the inverter L1 attempts to hold the node N1 high. The storage cell SC is designed to have a high static noise margin in order to hold data in a stable fashion. Therefore, this circuit is not capable of rapidly inverting the stored content of the storage cell SC only by discharging the node N1.
According to a first aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line, and (b-2) a write control line provided in corresponding relation to the write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, and (c-2) a first switch connected between the write data bit line of the one of the bit line groups corresponding thereto and the first storage node, the first switch being conducting only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active, wherein the write control line is active when an associated one of the bit line groups which includes the write control line is selected, and is inactive when the associated one of the bit line groups is not selected.
Preferably, according to a second aspect of the present invention, in the memory device of the first aspect, each of the bit line groups further includes (b-3) a write data complement bit line provided in corresponding relation to the write data bit line. The storage cell each includes (c-1-1) a second storage node receiving a logic complementary to a logic on the first storage node. Each of the memory cells further includes (c-3) a second switch connected between the write data complement bit line of the one of the bit line groups corresponding thereto and the second storage node, the second switch being conducting only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active. The write data bit line and the write data complement bit line have logics complementary to each other when an associated one of the bit line groups which includes the write data bit line and the write data complement bit line is selected, and have the same logic when the associated one of the bit line groups is not selected. The write control line has the exclusive OR of the write data bit line and the write data complement bit line in the one of the bit line groups.
Preferably, according to a third aspect of the present invention, in the memory device of the second aspect, potentials on the write data bit line and the write data complement bit lines are non-invertingly amplified and then exclusive-ORed.
Preferably, according to a fourth aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode connected to the write control line, and first and second current electrodes; and (c-2-2) a second transistor having a control electrode connected to the write word line, and first and second current electrodes. The first and second current electrodes of the first transistor and the first and second current electrodes of the second transistor are connected in series between the first storage node and the write data bit line.
Preferably, according to a fifth aspect of the present invention, in the memory device of the fourth aspect, the first switch further includes: (c-2-3) a third transistor having a control electrode receiving a logic complementary to a logic on the write control line, a first current electrode connected to the second current electrode of the first transistor, and a second current electrode connected to the first current electrode of the first transistor, the third transistor being different in conductivity type from the first transistor; and (c-2-4) a fourth transistor having a control electrode receiving a logic complementary to a logic on the write word line, a first current electrode connected to the second current electrode of the second transistor, and a second current electrode connected to the first current electrode of the second transistor, the fourth transistor being different in conductivity type from the second transistor.
Preferably, according to a sixth aspect of the present invention, in the memory device of the fourth or fifth aspect, the first current electrode of the first transistor and the second current electrode of the second transistor share one region with each other.
Preferably, according to a seventh aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode, a first current electrode connected to the write data bit line, and a second current electrode connected to the first storage node; and (c-2-2) a second transistor having a control electrode connected to the write control line, a first current electrode connected to the control electrode of the first transistor, and a second current electrode connected to the write word line.
Preferably, according to an eighth aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode connected to the write word line, a first current electrode, and a second current electrode connected to the write control line; and (c-2-2) a second transistor having a control electrode connected to the first current electrode of the first transistor, a first current electrode connected to the write data bit line, and a second current electrode connected to the first storage node.
According to a ninth aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line, and (b-2) a write control line provided in corresponding relation to the write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, and (c-2) a first potential setting section for providing a logic complementary to a logic on the write data bit line of the one of the bit line groups corresponding thereto to the first storage node only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active, wherein the write control line is active when an associated one of the bit line groups which includes the write control line is selected, and is inactive when the associated one of the bit line groups is not selected.
Preferably, according to a tenth aspect of the present invention, in the memory device of the ninth aspect, the first potential setting section includes: (c-2-1) a first potential point for supplying a potential corresponding to a first logic; (c-2-2) a first switch for controlling electrical conduction between the first storage node and a first connection point, depending on a logic on the write control line; and (c-2-3) a second switch for controlling electrical conduction between the first connection point and the first potential point, depending on both of the logic on the write data bit line and a logic on the write word line.
Preferably, according to an eleventh aspect of the present invention, in the memory device of the tenth aspect, the first potential setting section further includes: (c-2-4) a second potential point for supplying a potential corresponding to a second logic complementary to the first logic; and (c-2-5) a third switch for controlling electrical conduction between the first connection point and the second potential point, depending on both of the logic on the write data bit line and a logic complementary to the logic on the write word line.
Preferably, according to a twelfth aspect of the present invention, in the memory device of the ninth aspect, the first potential setting section includes: (c-2-1) a first potential point for supplying a potential corresponding to a first logic; (c-2-2) a first switch for controlling electrical conduction between the first storage node and a first connection point, depending on a logic on the write word line; and (c-2-3) a second switch for controlling electrical conduction between the first connection point and the first potential point, depending on a logic on the write control line and the logic on the write data bit line.
Preferably, according to a thirteenth aspect of the present invention, in the memory device of the twelfth aspect, the first potential setting section further includes: (c-2-4) a second potential point for supplying a potential corresponding to a second logic complementary to the first logic; and (c-2-5) a third switch for controlling electrical conduction between the first connection point and the second potential point, depending on both of a logic complementary to the logic on the write control line and the logic on the write data bit line.
Preferably, according to a fourteenth aspect of the present invention, in the memory device of the fourth or seventh aspect, the first transistor is an NMOS transistor formed on an SOI substrate; and a potential for alleviating a forward bias on the first current electrode of the first transistor and a body is applied to the write word line which is inactive.
According to a fifteenth aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, (c-2) a switch connected between the first storage node and a first potential point supplying a first potential corresponding to a first logic, and (c-3) a control device for permitting open/close control of the switch, depending on a logic on the write data bit line of the one of the bit line groups corresponding thereto when the write word line of the one of the word line groups corresponding thereto is active.
Preferably, according to a sixteenth aspect of the present invention, in the memory device of the fifteenth aspect, the switch includes (c-2-1) a first transistor having a first current electrode connected to the first storage node, a second current electrode connected to the first potential point, and a control electrode. The control device includes (c-3-1) a second transistor having a first current electrode connected to the control electrode of the first transistor, a second current electrode connected to the write data bit line, and a control electrode connected to the write word line.
Preferably, according to a seventeenth aspect of the present invention, in the memory device of the sixteenth aspect, the control device further includes (c-3-2) a third transistor having a first current electrode connected to the second current electrode of the second transistor , a second current electrode connected to the first current electrode of the second transistor, and a control electrode receiving a potential corresponding to a logic complementary to a logic on the write word line.
According to an eighteenth aspect of the present invention, a memory device comprises: (a) a plurality of write word lines; (b) a plurality of write data bit lines; and (c) a plurality of memory cells each provided in corresponding relation to one of the write word lines and one of the write data bit lines, each of the memory cells including (c-1) a storage cell including a storage node, (c-2) a first transistor, electrical conduction of the first transistor being controlled by a logic placed on the one of the write data bit lines, and (c-3) a second transistor, electrical conduction of the second transistor being controlled by a logic placed on the one of the write word lines, the storage node being connected through only in-series connection of the first transistor and the second transistor to a first potential point supplying a first potential corresponding to a first logic, the storage cell further including a third transistor having a first current electrode connected to the storage node, a second current electrode receiving a second potential corresponding to a logic complementary to the first logic, and a control electrode, and a fourth transistor having a first current electrode connected to the control electrode of the third transistor, a second current electrode receiving the second potential, and a control electrode connected to the storage node.
Preferably, according to a nineteenth aspect of the present invention, in the memory device of the fourth aspect, the storage cell comprises a pair of cross-coupled transistors.
Preferably, according to a twentieth aspect of the present invention, in the memory device of the fourth aspect, the first transistor and the second transistor differ in conductivity type from each other.
In the memory device according to the first aspect of the present invention, both of the write word line and the write control line are active in a memory cell to be written during a write operation, to connect the first storage node through the first switch to the write data bit line. Thus, it takes short time to invert the logic to be stored at the first storage node, independently of the logic placed on the write data bit line. On the other hand, the write control line is inactive in each of the memory cells which are not to be written. Then, the first switch does not connect the first storage node to the write data bit line. This reduces unwanted power consumption in the memory cells which are not to be written.
In the memory device according to the second aspect of the present invention, the write data bit line and the write data complement bit line are precharged in each of the unselected bit line groups. This precharge operation normally drives the write data bit line and the write data complement bit line to the same potential. Therefore, exclusive-ORing the write data bit line and the write data complement bit line inactivates the write control line.
In the memory device according to the third aspect of the present invention, the exclusive-OR is correctly provided even when the potential to be applied to the write data bit line and the write data complement bit line during the precharge operation is intermediate between two potentials corresponding to complementary logics.
In the memory device according to the fourth, seventh or eighth aspect of the present invention, the first switch is implemented by the use of the first and second transistors.
The memory device according to the fifth aspect of the present invention can avoid the reduction in the potential to be applied to the first storage node by the amount of the threshold voltage of the first and second transistors below the potential to be applied to the write data bit line. This eliminates the need to provide a circuit for increasing the potential on the write word line.
In the memory device according to the sixth aspect of the present invention, the first switch having a smaller area is implemented.
In the memory device according to any one of the ninth to thirteenth aspects of the present invention, both of the write word line and the write control line are active in a memory cell to be written during a write operation. In this case, the logic complementary to the logic on the write data bit line is provided to the first storage node. On the other hand, the write control line is inactive in each of the memory cells which are not to be written. Then, the first potential setting section does not place any logic on the first storage node. This reduces the unwanted power consumption in the memory cells.
The memory device according to the fourteenth aspect of the present invention can suppress an effective base current flowing between the first current electrode and the body of the second transistor when the write word line is inactive, even if the second transistor is formed on the SOI substrate, to thereby eliminate so-called xe2x80x9chalf-select write disturb.xe2x80x9d
In the memory device according to the fifteenth or sixteenth aspect of the present invention, when the write word line is active, the switch is open/close controlled depending on the logic on the write data bit line to control the electrical conduction/non-conduction between the first storage node and the first potential point. There is no path through which electric charges directly move between the first storage node and the write data bit line. Thus, the storage cell neither charges nor discharges the write data bit line in the memory cell to be written or in the memory cells connected to the same write word line as the memory cell to be written, thereby to avoid the unwanted power consumption. Additionally, the read operation from the memory cells connected to the same write word line as the memory cell to be written is performed rapidly.
The memory device according to the seventeenth aspect of the present invention can achieve on/off control of the first transistor with precision.
In the memory device according to the eighteenth aspect of the present invention, there is no path through which electrical charges directly move between the storage node and the one of the write data bit lines. Thus, the storage cell neither charges nor discharges the one of the write data bit lines in a memory cell to be written or in each memory cell which shares the use of the one of the write word line with the memory cell to be written. This eliminates unwanted power consumption. The storage cell comprises the cross-coupled third and fourth transistors to achieve area reduction by the area of two transistors per storage cell, as compared with a storage cell comprising a pair of cross-coupled inverters. Further, the storage cell in the eighteenth aspect can perform a rapid write operation.
In the memory device according to the nineteenth aspect of the present invention, the storage cell can achieve area reduction by the area of two transistors per storage cell, as compared with a storage cell comprising a pair of cross-coupled inverters, and also perform a rapid write operation.
In the memory device according to the twentieth aspect of the present invention, the worst value (maximum value) of the time required to stabilize the storage cell is less than that in a configuration in which the first and second transistors are of the same conductivity type.
It is therefore an object of the present invention to provide a technique for reducing unwanted power consumption while rapidly performing a write operation which inverts a stored content.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.